PIC18F14K50-I/SS【PDF 11/285 页】IC PIC MCU FLASH 8KX16 20-SSOP

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PIC18F/LF1XK50

DS41350E-page 108

Preliminary

2010 Microchip Technology Inc.

11.3.2

TIMER1 OSCILLATOR LAYOUT

CONSIDERATIONS

The Timer1 oscillator circuit draws very little power

during operation. Due to the low-power nature of the

oscillator, it may also be sensitive to rapidly changing

signals in close proximity.

The oscillator circuit, shown in Figure 11-3, should be

located as close as possible to the microcontroller.

There should be no circuits passing within the oscillator

circuit boundaries other than VSS or VDD.

If a high-speed circuit must be located near the oscilla-

tor (such as the CCP1 pin in Output Compare or PWM

mode, or the primary oscillator using the OSC2 pin), a

grounded guard ring around the oscillator circuit, as

shown in Figure 11-4, may be helpful when used on a

single-sided PCB or in addition to a ground plane.

FIGURE 11-4:

OSCILLATOR CIRCUIT

WITH GROUNDED

GUARD RING

11.4

Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

Timer1 interrupt, if enabled, is generated on overflow,

which is latched in the TMR1IF interrupt flag bit of the

PIR1 register. This interrupt can be enabled or disabled

by setting or clearing the TMR1IE Interrupt Enable bit

of the PIE1 register.

11.5

Resetting Timer1 Using the CCP

Special Event Trigger

If either of the CCP modules is configured to use Timer1

and generate a Special Event Trigger in Compare mode

(CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will

reset Timer1. The trigger from CCP2 will also start an

A/D conversion if the A/D module is enabled (see

Section 14.3.4 “Special Event Trigger” for more

information).

The module must be configured as either a timer or a

synchronous counter to take advantage of this feature.

When used this way, the CCPRH:CCPRL register pair

effectively becomes a period register for Timer1.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special Event Trigger, the write operation will take

precedence.

VDD

OSC1

VSS

OSC2

RC0

RC1

RC2

Note: Not drawn to scale.

Note:

The Special Event Triggers from the

CCP2 module will not set the TMR1IF

interrupt flag bit of the PIR1 register.

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